|
1255, Sacramento, CA-95825, U.S.A Phone: 916-925-2410 (H) |
ASHISH B. SAPRA E-mail:
ashishsapra@msn.com |
OBJECTIVE:
Seeking a Co-op/internship position
in the field of ASIC design/ Chipset design/ Test engineering which would
enable me to broaden my current skills and challenge my various abilities.
EDUCATION:
|
Masters
– M.S.Electrical & Electronics Engineering |
Expected December 2006 |
|
o
|
|
|
Bachelors – B.E.Electronics
|
June 2002 |
|
o
M.S.University of |
|
|
Bachelors – B.Sc. Physics
|
April 1999 |
|
o
M.S.University of |
|
COURSE WORK:
|
o
Advanced Logic Design |
o
Micro-Computer
System Design |
o
Advanced Timing Analysis |
|
o
CMOS
and VLSI |
o
Hierarchical
Digital Design |
o
Advanced VLSI Design |
|
o
VLSI
Design |
o
Advanced
Computer Architecture |
o
Analog
and Mixed Signal IC Design |
TECHNICAL
SKILLS:
|
o
HDLs |
: |
Verilog, VHDL |
|
o
Operating Systems |
: |
Windows 95/98/ME/NT/2000/XP/2003, MS DOS, Linux,
Unix |
|
o
Software Tools |
: |
Xilinx ISE, Modelsim,
Synopsys VCS Design Compiler & Analyzer, Synopsys Primetime(Exposure),
L-Edit Layout Tool, PSpice, OrCAD, Matlab(Exposure) |
|
o
Programming |
: |
Assembly Language(8085/8086),
C |
|
o
Applications |
: |
MS Office, MS Visio
Technical, Internet Explorer, Netscape Navigator |
|
o
Equipments |
: |
Logic Analyzer, Digital Oscilloscope,
Galep Programmer |
OTHER
SKILLS / ABILITIES:
o
Enthusiastic, Creative
troubleshooter/problem-solver, knowledge-hungry, self-starter, eager to meet
challenges and quickly assimilate newest and latest technologies, skills,
concepts, and ideas.
o
Quick learner who can rapidly
master all aspects of job with limited training.
o
Enthusiastic about applying
new technologies, enhancing current technical expertise, and applying
transferable skill sets.
o
Strong Project planning, good leadership, peer
evaluation and Coordination skills.
PROJECTS:
Advanced Logic Design:
o Design of Moore/Mealy finite state
machine for sequence detector using Verilog and Xilinx CPLD.
o Design of
4-bit matrix Keypad for LED’s as well as LCD using Verilog/VHDL and Xilinx
CPLD.
o Generation
of different waveforms and display them on logic analyzer.
o Display
number in scrolling fashion on LCD.
o Multiplication
of two 4-bit number and display the result on LCD using matrix keypad and
Xilinx FPGA.
o Write
data on all address of SRAM and display checksum of data on LCD.
o Copy the
content of Flash to SRAM and read content from SRAM and display it on LCD.
o Verilog
coding for ADC to Collect data by use of potentiometer and simultaneously store
it on SRAM and display it on LCD when another switch is pressed.
CMOS and VLSI:
o Design of
3-bit binary up down counter. L-edit was
used for layout
Micro-computer System
Design:
o ISA Card: Design a bus steering control logic
circuitry for an Intel 386 microprocessor and ISA Bus running at 8.333 MHz. Validation was done to support following
cycles.
·
1,
2, 4 byte read/write from 8 bit device
·
2,4
byte read/write from 16 bit device
·
read/.write
from 32 bit device
o PCI Card: Design of 32-bit PCI card and
has to perform PCI read and write with two data bytes transfers.
Hierarchical Digital Design:
o Modeling
of 32-bit ALU, sequence detector and code lock system using verilog.
o Modeling and
synthesis of 32-bit ripple carry adder using different hierarchical methods.
o Modeling
and synthesis of optimized pipelined matrix multiplier. Design a memory and read the two 32-bit 100
X 100 matrix elements from memory and write back multiplication result in
memory addresses.
Advanced Computer Architecture:
o Design and
simulation of 32-bit carry look ahead adder.
o Design and
simulation of 32-bit Optimized Multiplier, Divider, Floating point adder.
Projects Held under Graduate Apprentice:
o
Build RS232 to TTY Interface Cable.
o
Build RS232
o
Program Siemens Operating Panel in Visual C++.
RESEARCH PAPERS:
Design of DDR SDRAM:
o Double Data
Rate-Synchronous DRAM is
a type of SDRAM that supports data transfers on both edges of each clock
cycle (the rising and falling edges), effectively doubling the memory chip's
data throughput. Presentation on its functional description,
advantages, disadvantages and applications.
IDDq Testing:
o It covers in-depth research in the
area of IDDq fault modeling like stuck-at fault model, transistor fault model,
bridging fault model; IDDq test generation pattern like each test vector,
selective IDDq vector, supplemental IDDq vector; IDDq measurement techniques
like on-chip and off-chip measurement unit; and IDDq design for testability
structure.
Hyper Threading Technology:
o Describes the Hyper-Threading
Technology architecture, and discusses the micro architecture details of
Intel's first implementation on the Intel processor family.
WORK EXPERIENCE:
University Computing & Communication
Services, CSUS 02/27/2005 – Till date
Lab Assistant
o
Working as Lab Assistant with UCCS, CSU Sacramento
with good communication skills, strong technical support as well as customer
support.
o
Computer Assembling & Hardware/Software
Support
FAG
Bearings India Ltd.,
Graduate Apprentice
o
Repairing,
Testing, Installation & Maintenance of various AC & DC Drives.
o
Repairing of Different Statistical Calibrating
Systems which are used to calibrate the accuracy level of Product.
o
Repairing and testing of different SMPS.
o
PLC
and NC Handling & Programming Experience for Siemen’s STEP 5, STEP 7,
Mitsubishi’s
o
Knowledge of MMC which is used for Siemen’s automation
System operator panels.